120dB Pseudo-Logarithmic Amplifier

A project for ECE 547 “VLSI Design”
Fall Semester 2011 at the
Electrical Engineering Dept. of the
University of Maine

Designed by
Faisal Rahman

Computer chip

The overall design consists of a cascade of current limiting amplifiers followed by a difference amplifier. The pseudo-logarithmic amplifier accepts a single ended current input from 100pA to 100uA and produces a single ended voltage output that is pseudo-logarithmic representation of the input current. The rail to rail voltage of the amplifier is 3.3V, and the range of the output voltage is from 0.5V to 3V. An eleven stages configuration is applied to meet the desired dynamic input dynamic range of 120dB. The most important feature of these current amplifiers is that they are limiting. That is, there is a set value of current that cannot be exceeded no matter how great the input current may be. In this design the current is limited to 100uA.The design is implemented so the all eleven stages has a current gain of 4. Each amplifier has three outputs, Iout, Isum1 and Isum2. The Iout of the 1st amplifier is the Iin for the 2nd amplifier and so on. All the Isum1 and Isum2 gets added to give to logarithmic current output; Isum1 having a positive value and Isum2 having a negative value. These two currents are the inputs of the difference amplifier which provides a corresponding linear voltage from 0.5V to 3V. The bias of this design has been modified and was decided to do external biasing. Due to parasitic resistance in the lower side of the input current less than one microAmp the output voltage becomes non-linear. Based on the test data, the bias voltages will be determined and this information will be implemented in the next phase of the design.

The project report containing a description of the project and details of the design and layout will be available soon.

Fall 2011