10-bit D/A Converter for a 50MHz Direct Digital Synthesizer

VLSI Analog Design Project
ECE 547 — Spring 2006
Electrical & Computer Engineering Department
University of Maine

Designed by
Steve Fortune

other blocks desgined by:
Aravind Reghu (12-bit Pipeline Accumulator)
Ogy Nikolic (8-bit ROM Pointer)
Cyrus Miller and Anusha Ramanujam (4×64-bit ROM)

Figure 1 — Layout of 50MHz DDSThis IC generates a 25MHz sinusoidal waveform centered at 2.55V with an amplitude of 0.85V (Vpp = 1.7V) when given a 12-bit binary input that count from 000h through FFFh with transitions occuring at 50MHz. The major design blocks include a 12-bit Accumulator, 8-bit ROM Pointer, 4×64-bit ROM and a 10-bit DAC. See schematic in Figure 2 below.

Complete project details are available in the project report (PDF).