10 Bit, 50MHz, Pipeline A/D Converter

Dept.of Elec. and Comp. Engineering
University of Maine, Orono.
ECE 547, “VLSI Design” class — Fall 2002

Designed by
Alma Delic-Ibukic

Pipeline A/D converters are typically used in moderate resolution high speed applications. In pipeline architecture, several stages with a low resolution per stage are cascaded to obtain a high overall A/D converter resolution. This VLSI design project consists of a 10-bit, 50MHz, pipeline architecture A/D converter. The converter is implemented with a 9 stage pipeline architecture, 1.5-bit per stage. The design is based on a switch-capacitor circuitry. Each stage consists of a gain stage ( OTA  (designed by Erik McCarthy) and S/H switch capacitors), differential comparators (sub-ADC), and a sub-DAC. Intermediate bits (1.5 bits/stage) are not digitally corrected, instead they are the outputs of the converter. The die size is 1.5 x 1.5 mm and it is packaged in a 40 pin DIP. The project report (PDF) contains a description of the project, details of the design and layout, and test results.

Computer chip
August 2003