Flewelling
Analog Phase Locked Loop
A project for ECE 547 “VLSI Design”
Spring Semester 2007 at the
Electrical Engineering Dept. of the
University of Maine
Designed by
Greg Flewelling
This chip contains an Analog Phase-Locked Loop (APLL). The APLL is made of a Gilbert cell, off-chip low-pass filter, and a differential input, differential output voltage-controlled oscillator (VCO). There is a startup circuit for tuning the output to the appropriate frequency before releasing control to the APLL. Also include on the chip is an extra VCO and Gilbert cell.
The project report (PDF) contains a description of the project and details of the design and layout.
May 2007